1. Field of the Invention
This invention relates to logical verification of digital designs characterized by asynchronous communication between two or more clock sections. That is, the clocks in different systems or different sub-systems in a system may be running at different speeds and the phase relationship between the clock sections may be constantly changing. This condition is increasingly prevalent as cycle times decrease to allow local sections of logic to run as fast as they possibly can without being forced to run slower due to another section of logic or off chip logic which has a higher or lower maximum clock rate. Asynchronous clocking is also in wide use for communications chips tying multiple parts together, all of which may be running at different speeds. Under these asynchronous clocking conditions, the design may experience periods of metastability at the boundaries between clock sections. This may be due to variable phase relationship of the clocks, rise and fall times of signals, and setup times for capturing the data in the receiving clock section.
2. Description of Background
Hardware descriptions languages (referred to herein as “HDL's”) are used to design logic circuits and to verify the design correctness and behavior of logic circuits. This includes verifying asynchronous behavior, for example the asynchronous behavior observed on the IBM z-series processor, L2 cache controller and L3 memory controller interface. As a general rule, asynchronous behavior is included in the design to allow processors, cache controllers, and memory controllers to run at their individual, local optimum speed for each unit without concern for the maximum clock speeds of the other elements.
One problem is the difficulty encountered in detecting design problems on an asynchronous boundary between clock sections with variable phase relationships. This is especially severe in a cycle simulator because of the synchronous nature of the simulator engine itself. In a cycle simulator with a synchronous simulator engine, even if the clocks are run at different relative rates in the clock sections, they are still “synchronized” at the simulator clock boundary. As a result, some artifacts attributed to asynchronous boundary crossings may not present in the simulation, like glitches, different rising/falling edge times on individual bits in a multibit bus, and short pulse widths which may be missed by the logic on the receiving clock section.
Similarly, the metastability behavior of the asynchronous crossings was emulated using software working through the simulator applications program interface (API), but this solution does not match the performance of a HDL solution on a cycle simulator and provides extremely poor performance on a hardware emulator.